C_STEP Coplanar Step Parameters Notes Equivalent Circuit
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Coplanar Step C_STEP module represents a step in line width and/or line slot of a coplanar line. The dimensions of lines at both sides of a step are defined using data items addressed by C_ LTYP1 and C_TYP2. SL is the step length. L1 and L2 are the lengths of connected coplanar lines at ports.

Parameters  

Notes

• A negative value for L1 or L2 can be meaningful during the simulation. In such cases, the automated layout generation works incorrectly and the generated layout has to be edited manually. The minimum value for L1 and L2 depends on the metal layer oversize in the currently selected C_LAYER. In case of DEFAULT foundry, L1 and L2 should be greater than or equal to max(|cond_os|, |cond2_os|).
• C_LTYP1 and C_LTYP2 must have the same CEN_MET.
• A value of SL=0 is not possible, if W1+2S1 £ W2 (or W2+2S2 £ W1).
• The difference between the center line widths (W2-W1) has to be an integer multiple of DL. Otherwise the simulator will shift the line at port 1 by a half of grid size (DL/2). In this case the step will become asymmetrical and the user get the message: "(W2-W1)/DL no integer -> asymmetrical step". Please note that this change is not considered by layout generation. The layout of a step is always symmetrical.
• If W1+2S1+2GW1 ¹ W2+2S2+2GW2, there could be an step in the outer contour of the ground strips. In this case, the ground width of the line with smaller value of W+2S+2GW is increased, so that there is no step in the outer contour of ground planes. This change is considered by the simulation and layout generation.
• If W1<W2 and W1+2S1>W2+2S2 (or W2>W1 and W1+2S1<W2+2S2), the step in the inner contour of ground planes is shifted by SL. This change is considered by the simulation and layout generation.
• If L1 and L2 in selected C_GRID are not set to –1 or –2 (auto sizing), the minimum values for L1 and L2 are:

  L1min=max( W1+2S1+2GW1, W2+2S2+2GW2)

  L2min=8DL+SL

Equivalent Circuit  

For the modeling of the C_STEP element, a p-network is used. The equivalent circuit parameters are derived from quasi-static FD-calculations. The connected lines at ports are modeled as C_LIN elements and are represented by their characteristic impedances ZL1, ZL2 and phase constants b1, b2. There is no limitation due to the length of connected lines L1 and L2.